On the Radix-2 Syndrome Generators for Varshamov-Tenengolts-Coded Vertical Racetrack Memories

A promising candidate for 3-D solid-state storage is a vertical racetrack memory (VRM) which is capable of storing hundreds of bits within a tiny footprint. The stored bits are able to shift spintronically along the racetrack. However, their probabilistic movement inflicts positional errors, manifested as random bit deletions (or insertions) that necessitate Varshamov-Tenengolts (VT) codes which are able to correct these positional errors. VT syndrome generation (SG) is an iterative process and its latency grows linearly with the length of a VRM cell. In this article, we focus on the parallelization of SG, in order to bring a dramatic reduction in latency. We propose a radix-2 SG that processes a pair of data bits simultaneously in its compute engine, effectively reducing the number of iterations to half. The incident data block is partitioned and the two bits are selected from different partitions which are either stacked or folded. This partition space is explored with mathematical and architectural viewpoints in this work. The careful evaluation shows that a radix-2 folded SG is superior to other choices as it not only achieves the anticipated 50% reduction in delay, but also dramatically reduces the energy consumption when compared with recent state-of-the-art syndrome generators.