Fine-Grain Reconfigurable Logic Circuits for Adaptive and Secure Computing via Work-Function Engineered Schottky Barrier FinFETs

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky barrier (SB) FinFETs for sub-10-nm gate length. The study has three subsections. First, two-transistor (2T) and 4T and-or-invert (AOI)/or-and-invert (OAI) gates with select bits that allow multiple logic functions are introduced. Second, the use of WFE to create ultracompact reconfigurable logic circuits of fundamental operations (0, 1, OR, AND, NAND, NOR, and XOR) are explored via novel 2T, 3T, and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multistage circuits, such as compact full adders, are also modeled via TCAD simulations. Power
$\times $
delay product (PDP) figures and dc gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact 1-bit arithmetic logic unit (ALU), which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, addition, and subtraction) with three select bits using only 26 SB-FinFETs, saving a substantial amount of power and chip area. The tradeoffs between the number of metal work-functions used in the designs, circuit complexity, and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET-based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using
$\times 3$
to
$\times 10$
less power and between
$\times 2$
and
$\times 15$
less area than static CMOS counterparts. Although they suffer greater delays (
$\times 2$
–
$\times 5$
), the overall PDP performance remains comparable to conventional CMOS.