Standard Cell Library Enhancement For Mixed Multi-Height Cell Design Implementation

In current technologies, standard cell libraries are being designed with different cell heights for performance, area, etc. optimization. For better trade-off between area usage and performance of integrated circuit, these types of libraries are mostly used together in one design, however their mixed usage has many restrictions, such as minimum tile selection for each type of library, separate block creation and integration into top block, power and ground metal grid changes, etc. Proposed method is using special approach to multi-height cell libraries for increasing their cross-usage capability in one block without different height cell placement area separation. Along with this, special type of cells is created to fill empty areas after successful placement of cells. Experiments show, that with using proposed approach, standard cell design area can be optimized by about 19,2% compared to pure 12 track design and timing performance can be optimized by about 14.3% in comparison with pure 9 track design. However, runtime is increased by about 26.9% because of physical data post-processing and power usage is increased by about 12.8%, because of big drive cell usage.