Design Validation of Recurrent Signal Processor FPGA prototype

This paper describes the final stage of the FPGA prototype development of a recurrent signal processor. During the development of this prototype, a set of tools was created, based on which design verification was carried out. We describe the development process and the prototype validation methodology on a class of DSP tasks using a demo task of isolated word recognition. Taking the previously developed tools and methods for verifying software and hardware models, we have developed a specialized design validation tool. This solution made it possible to ensure the uniformity of the validation process for various types of architecture implementation and to establish the correctness of their operation.