Impedance Modeling of Three-Phase Grid-Connected Voltage Source Converters With Frequency-Locked-Loop-Based Synchronization Algorithms

With the increased installation of voltage source converters (VSCs) into the power grid, concerns about resonance/stability issues associated with interactions among converters, and between them and the ac grid is growing. The prevailing method for investigating these issues is the impedance modeling of VSCs, which involves linearizing all their control elements, such as their current control and grid synchronization system among others. In this process, most often a phase-locked loop (PLL) is considered for the grid synchronization of VSCs in the literature. The available options for the grid synchronization, however, are not limited to PLLs; a large number of frequency-locked loops (FLLs) for the grid synchronization of VSCs may also be found in the literature. The impedance modeling of three-phase VSCs equipped with FLL-based grid synchronization systems can be quite challenging as FLLs have different structures compared to PLLs. This article aims to address this difficulty. The general idea is obtaining the PLL counterparts of FLLs, which makes the VSC impedance modeling very straightforward. To make this idea clear, several case studies are presented and investigated.