Modeling the gated-diode response of an irradiated SOI back-channel interface

In this work the gated-diode technique has been applied to n-channel SOI MOSFETs that were part of a test vehicle used for a 0.25 /spl mu/m SOI CMOS product development. We have shown that the gated-diode technique is a powerful technique for the evaluation of the Si-film/buried-oxide interface, and that the technique is simple in measurement configuration. Our 2D numerical simulation of the SOI back-channel gated-diode results indicates that the back-channel radiation-induced interface state concentration can be modeled as an acceptor interface state at an energy of 0.7eV.