An Approach for Synthesis of Magnitude Comparators

The paper presents an approach for the synthesis of a magnitude comparator comparing two five-bit binary numbers. The magnitude comparator is implemented in Logisim and tested for different input combinations. Then the circuit is built in the environment of ISE Project Navigator needful for programming the FPGA-based laboratory board, developed at the University of Ruse and used in the educational process. The work is related to the project in the course “Pulse and Digital Devices” for students-bachelors of the specialties “Electronics” and “Internet and Mobile Communications”.