Test Coverage Analysis of DFT with EDT and without EDT Architecture

ATPG is one of the well-defined technique for generating test patterns for testing the chips. Today's world of SOC design environment, designs are complex so that the number of test patterns required for testing the chips increases. EDT (Embedded deterministic testing) is employed in order to reduce the test volume and reduced ATE memory usage due to large number of test patterns. This paper aims to determine, how well the EDT architecture performs in a DFT environment in terms of coverage for atspeed and stuck at fault model.