A Tunable Parameter, High Linearity Time-to-Digital Converter Implemented in 28-nm FPGA

This article presents a high linearity time-to-digital converter (TDC) with tunable parameters, based on a field-programmable gate array (FPGA) device. Specifically, a nonuniform monotonic multiphase (NUMMP) method is proposed to reestablish equivalent delay units with nonuniform delay time to overcome the limitation of the intrinsic delay and the uniformity of delay element in FPGA first. Then, the raw data frame composed of the equivalent delay units is marked by a time scale marking (TSM) method. Third, a feature extraction (FE) method is proposed to extract the marked raw data frame to form a feature frame, which can reduce the data volume by 79.1%. After that, the feature frames are decoded by a proposed coarse-fine decoding (CFD) algorithm, which can increase the decoding speed, shorten the dead time to 8 clock cycles and reduce the amount of decoding calculation by 80%. Finally, the proposed TDC has been verified with a Xilinx Kintex-7 FPGA. The measurement results demonstrate that the proposed NUMMP TDC with highly adjustable linearity and resolution has been realized. For a high linearity configuration with an LSB of 20 ps, the differential nonlinearity (DNL) and the integral nonlinearity (INL) are only +0.06/−0.05 and +0.08/−0.15 LSB, respectively. And for a high-resolution configuration with an LSB of 1.87 ps, the root mean square (rms) for the resolution can achieve 2.79 ps, and the values of the DNL and INL are +1.30/−0.54 and +3.51/−2.21 LSB, respectively.