A two-step folder for a high-speed CMOS folding-and-interpolating ADC

Optimum design flow of a two-step folder for the input-bandwidth extension of a CMOS folding-and-interpolating ADC is presented. We derived the minimum transistor sizes of the two-step folder and analyzed the effects of the offset voltage. We implemented a folding-and-interpolating ADC adopting the two-step folder in a 0.25 /spl mu/m 1P-5M CMOS process and got an experimental result of the input bandwidth of 50 MHz. This result verifies the design flow.