Design of a cycle-efficient 64b/32b integer divider using a table-sharing method

In new generations of microprocessors, the superscalar architecture is widely adopted to increase the number of instructions executed in one cycle. The division instruction among all of the instructions needs more cycles than the rest, e.g., addition and multiplication. It then, makes division instruction an important CPI (cycles per instruction) figure for modern microprocessors. In this paper, a radix 16/8/4/2 divider is proposed which uses a variety of techniques, including operand scaling, table partitioning, and table folding, to increase performance without the cost of increasing complexity.