A 0.01-mm2 1.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase

This paper reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) without both external reference and separate frequency detector. Specifically, our bang-bang phase detector incorporates the intrinsic three phases with a 2π/3 interval of the three-stage ring oscillator to deliberate the clock-selected strobe-point scheme, resulting in substantial hardware relaxation for automatic frequency acquisition. Together with the aid of a hybrid control circuit, the BBCDR can capture 6.4-to-8Gb/s data-rate variation automatically. Designed in a 65nm CMOS technology, our BBCDR achieves an energy efficiency of 1.2pJ/bit and 0.58UIpp jitter tolerance at 200MHz jitter frequency, while occupying a tiny area of ~0.01mm
²