A Single Node Upset Hardened Latch Design in NTV Regime

As CMOS technology scales down, state holding circuits are more prone to single node upset (SNU) due to the externally induced radiation phenomena. Therefore, the tolerance of the state holding circuits against SNU is strict requirement in nanoscale CMOS design. In this paper we present a unique high performance SNU hardened latch. The presented latch enhanced the soft error tolerance by using one storing element, in addition to one 2-input Muller C-element. We validate performance of our latch in industrial 65-nm and PTM 22-nm CMOS technologies. For an industrial 65-nm CMOS technology the proposed latch improves ∼ 76%, AEDP, in contrast to the recently reported latch. In 22-nm technology, our latch improves power dissipation and D-Q transmission delay ∼ 32 % and 16% over existing latches respectively.