VLSI architecture of a MPEG-4 visual renderer

This paper presents the architecture of a hardware block supporting the real-time rendering of all 2D natural or synthetic visual objects proposed by the MPEG-4 standard as well as sprite decoding. It is compliant to main profile, Level3 and hybrid visual profile. A software model allows us to validate the visual quality of the rendered scene. The complexity of this architecture is evaluated and the architectural choices are validated by means of simulations of a behavioral model.