A Review of the Electric Circuits for NBTI Modeling in p-Channel Power VDMOSFETs

This paper studies negative bias temperature instabilities in commercial IRF9520 p-channel power VDMOSFETs. Effects of these instabilities were extensively investigated under static and pulsed stressing conditions for various temperatures and voltages. It was noted that pulsed voltage stressing induces lower shifts as compared to static stressing under same conditions, because of partial recovery. In order to design appropriate modeling circuit for the threshold voltage shift, both degradation and recovery need to be examined and modeled. Based on these experimental results, several modeling circuits are proposed and analyzed. Purpose of all of the elements of the modeling circuits is explained in detail, as well as the development steps in circuit design. Concrete values of elements of modeling circuits are calculated. Results of modeling using different circuits are presented, and compared to the previously obtained results.