Reliability Evaluation of Digital Channelizers Implemented on SRAM - FPGAs

Digital channelizers are widely used in on-board processing (OBP) platforms to extract narrowband sub-channels from a wideband signal. The combination of a Discrete Fourier Transform (DFT) and a polyphase filter bank is recognized as an efficient structure for the channelizer. Field-programmable gate arrays (FPGAs) are a popular option for the implementation of digital channelizers due to their large computing capacity and good re-configurability. However, FPGA based digital channelizers will suffer single-event upsets (SEUs) on the space platform. This paper implements an 8-channel digital channelizer on Xilinx Zynq SoC, and performs hardware fault injection experiments to evaluate the reliability of the channelizer to SEUs on the configuration memory. In particular, the effect of SEUs on the DFT part and the polyphase filter bank part are examined separately. Experiment results show that about 75% of the SEUs will not affect the operation of the digital channelizer. For the DFT part, SEUs on most critical bits will cause wrong outputs of 8 or 4 sub-channels, and a very small portion of SEUs will cause no outputs of 8 or 4 sub-channels. On the other hand, the effect of the SEUs on the phase filter will be amplified by the DFT, so that all the sub-channels can be corrupted. These initial evaluation results can be valuable to guide the design of efficient fault tolerance schemes for parallel channelizers in future OBP platforms.