Effect of dimension of board and micro-bumps on interconnection stress under drop test

The reliability of electronic packaging is one of the most concerned issues, and the board-level drop test has become a key qualification test for assessing the impact reliability of electronic components. In literature, lots of work focus on PCB vibration patterns under different constraints and the influence of PCB dynamic response on solder joint reliability. Several work has compared the package component life with respect to different JEDEC standard boards. They found that the A-type(100x48mm) test board was prone to be failure, and the C-type(77x77mm) test board had longer life. Thus, this work is aiming to further evaluate the influences of variant board on the impact performance of solder interconnects. It was carried out by analyzing the dynamic response of PCBs with different form factors and discussing the effect of the dimension of Cu pillar, IMC and solder layer in orthogonal experiments. Firstly, ANSYS/LS-DYNA software was employed to obtain the X-direction strain curve at the center of PCB bare board with three aspect ratios. The strain curve at the center of PCB revealed more fluctuation as the aspect ratio decreasing, and implied the PCB dynamic response would affect solder joint stress. Through modal analysis and FFT, this phenomenon was mainly attributed to the superposition of mode shapes. Secondly, we conducted an orthogonal test to investigate the influence of size of Cu pillar, IMC and solder layer on the stress of interconnection layer. The Cu pillar on substrate side had the most significant effect on the stress level of solder layer. As the height of Cu pillar increased, the stress of solder layer decreased. Finally, drop test was performed for samples with Cu pillar being 15um and 30um in height and the drop life was calculated. The Weibull probability distribution diagram showed that the experimental results were consistent with our simulation.