Research on Wire Sweep of Integrated Circuit Packaging Based on Three-dimensional Flow Simulation

Semiconductor manufacturing technology is becoming more and more rapidly. In the process of Integrated Circuit (IC) encapsulation, when wires contact each other, it will cause short circuit. Wire sweep has become the main factor affecting the reliability of the product. Therefore, it is a great challenge to master wire sweep in IC packaging process. This paper takes Low Profile Fine Pitch Ball Grid Array (LFBGA) as the research object, applies moldex3D three-dimensional flow simulation technology to simulate the molding process of electronic products, and predicts the wire sweep problem that may occur in the molding process. The simulation results are compared with the actual experimental results, which shows that there is a good consistency between the two results. The research results show that the wire is close to the packaging gate, and the wire sweep is large; the wire is perpendicular to the melt front flow direction; therefore, when the IC packaging wire layout, long wires are located under the chip (far away from the gate), and short wires are located above the chip (near the gate), so as to reduce wire sweep. Secondly, the flow simulation of packaging products was carried out by changing the epoxy molding compounds, and the results of mold flow analysis of different molding compounds were compared. It was found that the epoxy molding compounds with higher viscosity had greater drag force on the wire, and the molding compound with higher viscosity had greater wire sweep than those with lower viscosity. The problem of wire sweep in IC packaging could be improved by selecting the epoxy molding compound with lower viscosity. This study has a certain reference value and guiding significance for the design and improvement of IC packaging.