Study on Gold Wire Sweep in Cantilever Chip-Stacked Package during Molding Process

With the continuous improvement on the function of electronics, the IC integration density is gradually increased. Meanwhile, the stacked chip packaging technology appeared to meet the requirements of chip integration. Among them, the cantilever stacked chip structure not only increases the package density, but also satisfies the need of vertically integrated chips with the same size. However, the gold wire sweep induced during the transfer molding process is still one of the critical issues for the reliability of the cantilever stack structure. Therefore, it is of great significance to explore the wire offset in the process of transfer molding to enhance the reliability of stacked chip packaging. In this paper, a mold-flow analysis model of cantilevered chip-stacked structure is setup. The viscoelastic properties were measured by using a DMA analyzer. For studying the deviation of wire loop in transfer molding, the process parameters including the molding temperature, filling time and melt temperature are analyzed by finite element simulation. Firstly, the effect caused by different positions of the gate on the wire offset also is studied. Secondly, the influence of the above process parameters on the position deviation of gold wire is studied following an orthogonal experiment route. The results show that the inhomogeneous temperature field caused by transfer molding has an affect the quality of the chip wire bonding, while the melt temperature has a great influence on the wire offset. Due to the influence of the flow rate of transfer molding, the closer the wire to the gate position is, the larger the offset will be, especially for the wire perpendicular to the gate position.