Studies on the Effects of Soldering Layer Structures on TEC Module Performance and Thermal Stress

Effects of soldering layer structures on the performance and thermal stress of thermoelectric cooling device (TEC) were studied by employing a three-dimensional finite element electric-thermal-mechanical modeling method established via COMSOL simulations. AuSn eutectic alloys and SnSb soldering were applied as joints to connect TE legs and metal bonded ceramic substrate (MBCs) for TEC's hot and cold ends, respectively. The temperature and stress distribution effects of the device based on different soldering layer structures were analyzed. The soldering layer structures include thickness, void size, number of voids, and void distribution. The results showed the maximum heat dissipation rate (Q
max
), the maximum temperature difference(ΔT
max
), and the related coefficient-of-performance (COP) of the device are decreased due to the reduction of the thickness of the soldering layer and the number of voids. Also, the more voids in the soldering layer greatly enhanced the maximum stress and temperature gradient. This enhancement will be more obvious when the voids stayed at the edge of the soldering layers.