Research on Double-Layer Networks-on-Chip for Inter-Chiplet Data Switching on Active Interposers

The chiplet-based heterogeneous integration technology implemented on active interposers has been developing rapidly in recent years. However, as the bit widths of interactive data packet is getting larger and larger, for example, the bit widths of HBM (High Bandwidth Memory) has reached 1024 bits, the enormous wiring resources required for parallel data exchange and the complexity of wiring, as well as crosstalk issues inducted by high density interconnection, have necessitated the shift from parallel to serial mode data transmission, so as to effectively mitigate the intimidating challenges from exponential increase of wiring resource demands and interconnection density. However, the advantage of serial transmission is obtained at the cost of several signal integrity and power integrity issues brought by the steep rise/fall edge of the high-speed waveform, in addition to relatively reduced transmission bandwidth under certain occasions. As the bit width continues to increase, this cost becomes more and more unacceptable. NOC (Networks-on-chip) is one of the potential options to solve this problem. This paper proposes a new NOC architecture that is 2D-Mesh structured with a socalled “data station” core, featuring dual-port RAM. Compared with the traditional single-layer NOC, this scheme adopts a double-layer structure, in which the top layer is a network with four dual-port RAMs as the data storage center and circuit-switch as the data exchange network, responsible for data transmission. The bottom layer is a traditional packet-switch NOC used for address packet exchange. The advantage of this design scheme is a largely reduced resource and power consumption of the NOC, making the NOC more attractive for 2.5D integration, especially those based on active interposers.