Precision and performance of numerically controlled oscillators with hybrid function generators

Numerically Controlled Oscillators (NCOs), bringing together in a hybrid scheme both ROM lookup tables (LUT) and hardware implementations of the iterative CORDIC algorithm for sine/cosine function generation are investigated. This scheme combines the respective advantages of (i) fast access and power efficiency of reasonably sized LUTs and of (ii) in principle arbitrary precision obtainable from a rigorous iteration algorithm. Systematic studies using hardware description language (HDL) models and synthesis lead to optimum LUT/CORDIC ratios, which minimize power consumption and silicon area for a given operating clock frequency. First order error models are presented as guidelines for choosing internal NCO parameters, as word lengths and the number of CORDIC stages for a given amplitude resolution. The NCO models are synthesized in a 0.35 /spl mu/m CMOS standard cell target technology. Two clock frequencies, 200 MHz and 20 MHz, implying maximum signal frequencies of about 70 MHz and 7 MHz, were implemented as 'high' and 'moderate' performance benchmarks, respectively. Both an on-chip 12 bit digital-to-analog converter (DAC) and an external (commercial) 14 bit DAC permit the microelectronic circuit to serve as a complete sine signal generator for clock frequencies up to 200 MHz.