High performance silicon-based substrate using buried PN junctions towards RF applications

This paper shows the potential of buried PN junctions as a substrate interface passivation solution to increase the effective resistivity (ρeff) figure of merit of a High-Resistivity (HR) substrate suffering from Parasitic Surface Conduction layer (PSC). We characterize Coplanar Waveguides (CPW) in order to monitor the substrate frequency response. We demonstrate that this method can be implemented using an industrial process with an effective resistivity reaching 2kΩ.cm with 0.1 dB/mm loss at 6 GHz for a HR+PN substrate. This method is suitable for local PSC passivation, targeting advanced SoC (System-on-Chip) in FD-SOI technology for next wireless communications generations.