Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits

The integrated circuit (IC) products fabricated in the scaled-down CMOS processes with higher clock rate and lower power supply voltage (V
_DD
) are more sensitive to the transient/switching noises on the power lines with the parasitic inductance induced by the bonding wire. The typical method to suppress the power line noise is to add on-chip decoupling capacitors. Meanwhile, electrostatic discharge (ESD) is also a challenging issue on IC reliability in advanced CMOS technology. For the ICs fabricated in an advanced process, with the thinner gate oxide, the circuits are particularly vulnerable to the charged-device model (CDM) ESD events. However, there was very limited research to investigate the ESD robustness on the decoupling capacitors, especially during the CDM ESD events. In this work, the CDM ESD robustness among different types of decoupling capacitors in ICs was investigated in a 0.18-
${\mu }\text{m}$
CMOS technology.