Understanding and addressing the noise induced by electrostatic discharge in multiple power supply systems

The design of on-chip ESD protection has become increasingly difficult and critical because of shrinking device feature sizes, high operating speed, and system on a chip (SoC) environments. A complex ESD protection network in an SoC can cause the degradation of circuit performance during normal operation. The loss introduced by ESD stress and protection networks is defined as ESD noise. In this paper, we present the generation and characterization of three different types of noise induced by ESD. The effect of ESD protection networks on sensitive circuits is investigated with a test chip processed in a 0.18 /spl mu/m CMOS technology. Experimental results suggest appropriate optimization of a tradeoff between ESD robustness and power supply coupling. It is important to note that, for mixed-signal design, the performance of a sensitive circuit is highly dependent on the ESD noise generated in the vicinity of the sensitive circuit, as well as circuit design techniques.