A New Accelerator for Convolution Neural Network

Deep learning and neural network technologies have surpassed traditional algorithms in many applications and have been increasingly used. Neural network algorithms require a lot of computing operations and have high requirements for hardware. Hardware accelerators are getting more and more attention. To design a high-performance convolutional neural network accelerator, this paper proposes a new accelerator circuit design method. The accelerator is programmable and supports layer-by-layer optimization for the CNN network, which realizes the better acceleration scheme for the computing and storage requirements of a specific network. The accelerator provides the ability to quantize different types of data to half-precision, which can reduce memory access. The accelerator can reach a peak performance of 211GOP/s under a 40nm SMIC CMOS process at 200 MHz operating frequency. A VGG16 network is implemented on our accelerator, and the delay of the convolution operation is 442.7 milliseconds.