Parallel Conflict-Free Ordered Access Memory Device

In this article, we propose the architecture of ordered access memory (OAM) device after examining the known methods of memory access, memory organization and related disadvantages. This memory device works with arrays of data and provides conflict-free parallel access. In this memory, data is identified by an index identifying column and row numbers of this data in the output data array. In the write mode, the indices are written to memory together with the data. In the read mode, the data are read from memory in an order specified by values of the assigned indices. This enables the disintegration of the data ordering apparatus and eliminates the need to store the addresses of the locations where the data are placed, as well as the need to submit the address to the address entries when writing and reading data. The approach to the design and use of this type of memory are described. The structural organization of the OAM device and its operation in the write mode and read mode are presented. Evaluation of the OAM device parameters and its comparison with other types of memory is performed. The OAM device was implemented in FPGA and the implementations results are explored.