Every Clock Counts – 41 GHz Wide-Range Integer-N Clock Divider

Current clock divider architectures suffer from either inflexible divider ranges or slow performance due to long logic paths. When implementing Compressed Sensing (CS) signal acquisition for systems operating at mm-wave Radio Frequency (RF), both flexibility and operation at the limits of the technology node are required. We propose a configurable integer-N clock divider architecture with synchronous reset that satisfies this need. With a wide divider range of S = 8. . . 1048583, an output duty cycle of 50% is guaranteed for even, and approached for odd divider factors. The architecture is suited for operation with very high input clock frequencies, approaching the transit frequency of the technology. The key to construct our design is a serializer based approach, that enables the control logic to operate on two levels of lower frequencies. A symbol generator provides the output symbol stream. Internal clocks are derived directly from internal state vectors. In this way, the 20 bit divider range is achieved with only 22 Flip Flops (FFs) (excluding the serializer) and no combinatory logic in the fastest clock domain. We demonstrate our architecture in 130nm SiGe BiCMOS technology using Positive Emitter Coupled Logic (PECL). We show that transistor-level simulation using calibrated fab models confirms successful operation up to f0=41.70 GHz which corresponds to approximately equal to 1/6th of the process transition frequency. At a die area of 0.06mm(exp 2) (including serializer), our design draws approximately equal to 225 mW from a 2.50 V supply.