Design and Optimization of a Control Algorithm for a Digital Low-Dropout Regulator in System-on-Chip Applications

The System-on-Chip (SoC) solutions have gained more importance in the field of microelectronics in the past years. The aim of this work is to develop an algorithm for a digital low-dropout regulator (DLDO) for a near-threshold / low supply voltage application. The developed LDO is fully synthesisable and has a high robustness. In the work, simulation models were developed for a combination of a 9-bit-Successive-Approximation-Register (SAR) and a proportional–integral–derivative (PID) controller. In addition, research and optimizations were carried out regarding the phase shift for better control of the PID controller, the switching between the two algorithms and the stability of the digital LDO. The design is implemented in a commercial CMOS technology, with the input supply voltage from 0.85 V to 1.8 V. The input voltage range of the developed design ranges from 0.9 V to 1.8 V and the power consumption is smaller as 10muW at an operating voltage of 0.9 V. In order to achieve a trade-off between a fast settling for large transient and a low ripple at DC, a combined algorithm of a SAR and a PID controller is implemented. We have also optimised the performance for a wide input voltage range (0.9 V to 1.8 V), fast settling time (50 mus at 4 MHz, 1.2 V) and stable setting (0.79 V to 0.84 V at 4 MHz, 1.2 V). The clock and the power consumption are also reduced (average <10 muW with 0.9 V VDC and 4 MHz, while the output power is between 10 muA and 320 muA using constant load.)