Analog Circuit Abstraction to SystemC-AMS Secured by Affine Forms

Formal verification of analog circuits still suffers from a lot of challenges. The continuous nature of the variables along with the well-known state space explosion problem obstruct most verification approaches. Using behavioral abstraction, a circuit can be verified to some extent, however, the quality of the results is limited to the accuracy of the abstract model. To solve these problems, we propose an automated abstraction methodology that generates from transistor-level Spice netlists accurate models at the system level in SystemC-AMS. The models are deployed as hybrid automatons (HAs) with reduced complexities and linear system equations. Further, to compensate for modeling errors resulting from the abstraction technique, an extended version of the approach utilizes affine forms to generate models that produce bounded results during symbolic simulations.