Modeling and Optimization of Supply Sensitivity for a Time-Domain Temperature Sensor

This paper presents a methodology for modeling and optimizing the supply sensitivity for a time-domain temperature sensor. Many modern System-on-Chip (SoC) designs integrate multiple functional blocks, such as sensors, power management units (PMU), and wired/wireless communication interfaces. In- terference on the supply line between such blocks becomes critical, since it has a significant impact on sensor performance. Many state-of-the-art designs utilize supply sensitivity as a sensor parameter to describe the immunity to supply interference. Therefore, modeling and analysis of this parameter to optimize sensor performance is needed. This paper begins with the modeling of the common time-domain temperature sensor, while an instance of the model is precisely created with extracted parameters. Additionally, verification is performed by comparing the model with a transistor-level design. Finally, the optimization methodology for supply sensitivity improvement is discussed. The results show that the DC supply sensitivity is significantly reduced by a factor of 41. With the proposed methodologies, a further AC supply sensitivity can be analyzed and optimized, so that sensor performance in SoC designs can be improved.