Qubit Gate Quality Loss Through Circuit Parasitics and Noise

This work aims to find signal sequences that implement high-quality logic gates for single GaAs qubits in a quantum computer. To achieve that an optimization of the gate quality with a scalable electronic architecture in mind is done. In addition, a behavioral model of the qubit and the control electronics in the Q-Interface is implemented. The electronic model includes typical integrated circuit impairments such as process variations and parasitic capacitors. While the initial quality of the optimized gates is high, simulations with the implemented model show partly large quality reductions for some impairments. A major quality loss is for example caused by parasitic capacitors, but some non-ideal effects can be mitigated through pre-distortion, among others.