Characterizing the Output Load Transient Based on a New Output Filter Circuit Extraction for CPU VRM Design

To meet Intel CPU VRM design specification in terms of output load transient, the conventional solution based on practical firmware tuning and spice netlist-based filter circuit simulation is verified not to be a good solution due to the unavailability of perceiving the physical insights for the output equivalent filter circuit. This poses challenges on the task of load transient optimization practically. This paper introduces the solutions of characterizing the load transient behavior by two approaches, the first one is based on the calculation of small signal model for output impedance, the focus secondary one is based on the circuit simulation with a new extracted equivalent output filter circuit. To correlate this, experiment based on TI VR13.HC PVCCIN prototype board is conducted, the validation shows that the proposed solution is valid to guide the practical design.