Guiding DART to Impact — the FPGA SoC Design of the DRACO Image Processing Pipeline

The Double Asteroid Redirection Test (DART) is NASA’s first planetary defense mission, scheduled to launch in late 2021 / early 2022. The spacecraft carries a single instrument, the Didymos Reconnaissance and Asteroid Camera for OpNav (DRACO). During the mission, DRACO imagery is used to guide the spacecraft to its target - the smaller asteroid, Dimorphos, of the Didymos binary asteroid system. The impact with Dimorphos will be observed from Earth and will validate key parameters of kinetic deflection mission design. Unlike a traditional instrument, DRACO performs most of the image processing onboard the spacecraft, in the spacecraft avionics. It is implemented within the Field Programmable Gate Array (FPGA) residing on the Single Board Computer (SBC) in the DART Processor Module (PM). As the DART SBC FPGA is a complex System on a Chip (SoC), implementing both the traditional spacecraft data systems functionality as well as the DRACO image processing functionality, the design was partitioned in sub-components for development by multiple teams. This paper focuses on development of the DRACO Image Processing Pipeline (DRIP) component of the FPGA. In particular, it explores the subtleties of interfacing to the instrument data stream, the image processing functionality, data handling, storage, data movement, and the embedded LEON3 processor. Novel aspects of the DRIP implementation include a one-pass Connected Component Analysis (CCA) engine, low-latency packet streaming capability, software-managed Command & Data Handling (C&DH), and a unique triple-buffering architecture for off-chip buffering and image data calibration. Also discussed are testing and verification efforts, which presented unique challenges due to the volume of data and the real-time aspects of the image processing pipeline.