Radiation hardened VHSIC CMOS/SOS process

Summary form only given, as follows. A vertical wall mesa process has been used to fabricate radiation-hard CMOS/SOS circuits for military applications. However, scaling of this process to smaller geometry has to include not only lateral dimensions but also vertical dimensions. For 1.6- mu m design rules, a radiation-hard process has been developed with 1.25- mu m effective channel lengths and 250-AA gate oxide. Two asynchronous 16 K SRAMs with 2.0- mu m and 1.6- mu m design rules, respectively, were used as test vehicles along with an extensive design rules verification module and a radiation test module. A defect monitor structure was also incorporated for process monitoring, failure analysis, and yield prediction. Gate oxide reliability was greatly improved by treating the edges of vertical islands using a modified isolation oxidation technique. Threshold voltage shifts as low as -0.3 V and -0.5 V at 1 Mrad (SiO/sub 2/) total dose for nFETs and pFETs, respectively, were achieved. A low radiation-induced edge leakage of 15 nA/edge, primarily due to thin gate oxide, was also achieved. 16 K SRAM functionality beyond 1 Mrad total dose was demonstrated.