A Design Technique for Delay and Power Efficient Dadda-Multiplier

In this research paper, the technique for the design of a fast multiplier is proposed by using two different techniques. A 4:2 compressor is used for power-efficient row compression in the proposed model, whereas for faster final summation, a carry-select adder has been used. Based on the above technique, a 16-bit Dadda-multiplier is proposed and its performance is analyzed by comparing it with the standard 16-bit Dadda-multiplier which normally uses carry-look ahead adder. The time delay of carry-select adder is improved when compared to carry propagate adder. The result depicts that the proposed 16-bit Dadda-multiplier is 4.85% power efficient and 63.4% time delay is improved. The simulation of the proposed multiplier is carried out using Verilog HDL in Xilinx ISE Design Suite 14.7.