Radiation hardened 16 K VHSIC CMOS/SOS static RAM

Summary form only given, as follows. A 16*1 static RAM utilizing a radiation-hardened VHSIC CMOS/SOS process and tolerant circuits to achieve functionality beyond 1 Mrad total dose are reported. The RAM is completely static, using asynchronous circuits and requiring no clock inputs. Key circuits were designed to be tolerant of radiation-induced threshold voltage shifts and leakages. Two versions of the design were made along with process test structures and design rule verification modules. The two versions use 2.0- mu m and 1.6- mu m design rules, respectively. Address transition detectors were used to eliminate static bit-line clamps and maintain low operating current, typically under 3 mA. Circuits were designed to ensure that integral precharging did not cause glitches on the output pin. Special test patterns were used to verify that no access time 'push-out' occurs from address skew. Typical access time for 2.0- mu m design rules is 45 ns. The design generally uses conventional full CMOS logic for tolerance to postradiation leakage and threshold voltage shifts. However, the bit-line/sense amp circuitry and an internal read bus required other methods to achieve both high speed and tolerance.