Hardware Implementation of a Chaos Based Image Encryption Using High-Level Synthesis

In recent years, the use of digital images in data transmission networks and digital devices has increased greatly. Therefore, the security of images in transmission or storage has become very important due to security attacks. For this reason, cryptography is used to protect images from unauthorized access and attacks. In this paper, an image encryption algorithm using chaos theory is proposed in which, besides providing the appropriate level of security, the speed of encryption operations is also considered. The 1D tent map is used for the encryption process. Its security analyses have been performed to verify its efficiency in terms of security. The hardware implementation of the algorithm was performed on FPGA with the help of high-level synthesis (HLS), architectural techniques, time and resource optimization. Based on our experimental results, the hardware designed for image encryption is robust in terms of security and it can achieve an encryption and decryption time of 21.14 milliseconds for an image with a size of
${256\times 256}$
.