FPGA-ENABLED REAL-TIME POWER GRID SIMULATION USING GRID PARTITIONING

The high penetration of Distributed Energy Resources (DERs) and the IoT devices in the grid, as a result of policy regulations and economic considerations, physically located everywhere, in all shapes and sizes, both in front (FTM) and behind the meter (BTM) are fundamentally transforming the grid into a decentralized network of new grid assets that participate in multiple hierarchical energy markets. This transformation, however, creates challenges that needs to be managed. In order to adequately capture the transient behavior of the various grid components, detailed component models and Real-Time (RT) simulations are required. Leveraging their inherent parallelism capabilities, FPGA platforms help to achieve high-speed simulation execution, becoming a useful validation and planning tool for power grid management. However, the hardware utilization in these solutions is directly proportional to the size of the network under test, leading to expensive and hardly scalable architectures unsuitable for the simulation of large scale power networks. In this paper, a novel technique is presented, which aims to reduce the FPGA's resources utilization in distribution power grids. There are cases where part of the network under test can be partitioned in a number of identical subnetworks, whose output can be calculated by the same hardware module and thus lead to hardware utilization reduction. As proof of concept of the proposed approach, the implementations of a microgrid with and without applying the partitioning technique are demonstrated and compared in terms of accuracy, simulation speed and FPGA resources utilization.