Electrical Characterization and Benchmarking of Polylithic Integration Using Fused-Silica Stitch-Chips With Compressible Microinterconnects for RF/mm-Wave Applications

A polylithic integration technology is demonstrated for seamless stitching of chiplets of various functions, including RF, analog, and digital chiplets. In this technology, stitch-chips with compressible microinterconnects (CMIs) are used for low-loss, low-parasitic, and dense interconnection between chiplets. The modeling, fabrication, assembly, and characterization of a set of testbeds using fused-silica stitch-chips with integrated CMIs are demonstrated in this article. A 500-
$\mu \text{m}$
-long stitch-chip signal channel is measured to have less than 0.42-dB insertion loss up to 40 GHz with minimal parasitics (
$4.68~\Omega $
at 28 GHz,
$4.99~\Omega $
at 39 GHz, 359 pH up to 40 GHz, and 62 fF up to 40 GHz). Moreover, CMIs’ S-parameters are extracted by the L-2L deembedding technique up to 40 GHz. CMIs exhibit less than 0.2-dB insertion loss up to 40 GHz with better than 16.2-dB return loss. Furthermore, benchmarking to other interconnections is presented in terms of loss and parasitics. Compared with conventional silicon-based interconnection, the data suggest that the fused-silica stitch-chip-based interconnection reduces the insertion loss by approximately 3.8-dB at the 28- and 39-GHz frequency bands. The stitch-chip interconnection has a similar insertion loss as glass interposer, organic substrate, and integrated fan-out (InFO) with the benefit of simple rework.