Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs

Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations (PVs) and aging effects manifest themselves as gate delay shifts, which in turn cause variability of circuit timing (timing variability). Required for dealing with the impact of timing variability better, detailed evaluation and analysis of circuit timing for VLD are actually not straightforward. In this article, we present a systematic methodology for analyzing a VLD circuit and identifying critical one-cycle and two-cycle paths/gates. Based on the criticality analysis, a gate sizing framework using particle swarm optimization (PSO) is proposed. Our objective is, in a less pessimistic fashion, to make constructed VLD circuits better (less vulnerable to timing variability). The experimental results show that the proposed framework can generate extra timing margins for VLD, such that process-induced error rate can be reduced to 0%–0.1% under 10% variability in gate delay. On average, an extra timing margin of 11.48% can be obtained without lengthening the clock period, and 1.52% area can be reduced simultaneously.