Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs

In sub-1-V CMOS designs, especially around 0.5-V CMOS designs, on-state drain current of MOSFETs shows positive temperature dependence, being different from the negative temperature dependence in the conventional voltage designs. Combined with low threshold voltage less than 0.2 V, the possibility of temperature instability increases. This paper describes possible temperature instabilities in the low-voltage regime by using circuit simulation environments incorporating temperature change in time and experiments using MOSFETs and the 32-bit adder circuit in quarter-micrometer CMOS technology with a low threshold voltage of 0.25 V.