Stochastic Rounding: Algorithms and Hardware Accelerator

We present algorithms and a hardware accelerator for performing stochastic rounding (SR). Our main goal is to augment the ARM M4F-based multi-core processor SpiNNaker2 with a more flexible rounding functionality than is available in the ARM processor itself. The motivation of adding such functionality in hardware is based on our previous results showing improvements in numerical accuracy of ODE solvers in fixed-point arithmetic with SR, compared to a standard round to nearest mode (RN) or bit truncation. Performing SR purely in software can be expensive due to requirement of multiple masking and shifting instructions, and an addition operation per each rounding. Also, saturation of values is included since it is required on overflows, which is common in fixed-point arithmetic due to a narrow dynamic range. The main intended use of the accelerator is to round fixed-point multiplier outputs, which are returned unrounded by the ARM processor in a wider fixed-point format than the arguments. The proposed accelerator is not specific to SpiNNaker, and is a generally applicable rounding unit provided a pseudorandom number generator is available that can supply random bits to it. Additionally, to the best of our knowledge, this is a first exploration of a stochastic rounding accelerator with a programmable bit position and multiple data type support.