Low power and single multiplier design for 2D convolutions

Practically, the concept of convolution reverts to the features where transformations and mathematical estimations for filters are designed. Each such filter and their operations are intended to perform real time applications that would suggest the different sections of the domains in embedded systems. One such application is for Digital signal & Image process. Currently the design on Convolutions are intended with filtering of the images with edges and other detection kernels. The proposed design implements the 3X3 kernel with 32x32 image size and 16 bit storage of data input conditioning with 9x16 convolution filter as modelled using Verilog. Here our design impacts on the improved power reduction factor based on the architecture design of the Convolutions with single multiplier ensuring the convolution stage with minimalistic features improvised on convolutions. Our design provides a 43.11 percentage reduction of power with dynamic scenarios of each of the data logics, signal and design elements using Verilog (Xilinx HDL).