A Novel Method to measure PLL Bandwidth in a 5G RF transceiver

Integrated PLLs are, nowadays, a part of all high-performance RF SoCs. This is required due to increasing system bandwidth requirement with every generation of wireless transceivers. The analog front-end converters (ADC and DACs) need to be clocked at higher clock rate. Some transceiver architectures involve analog mixers which also involve high frequency clock generation. Integrated On-Chip PLLs are needed for sampling clock or mixer clock generation for these systems. PLL uses a feedback control loop to lock the phase of the internal voltage-controlled oscillator with an incoming low frequency reference clock. The bandwidth of the loop filter used in the PLL is important to ensure the noise performance of PLL. Measuring the PLL bandwidth is not easy without extra DFT blocks and dedicated test points. If the RF transceiver has multiple analog PLLs, this can be difficult. This paper proposes a non-intrusive method to measure PLL bandwidth in RF transceivers.