An Approximate Symmetry Clock Tree Design with Routing Topology Prediction

With the technology scaling, a simple clock tree can hardly handle the complex situations in a modern System-on-Chip (SoC), such as thousands of clock sinks, multiple process, voltage and temperature (PVT) corners, and several clock domains. To transform a single tree problem into sub-tree problems, the hybrid clock tree which consists of a top-level tree and several local trees is becoming the promising structure for timing closure due to its flexible timing characteristics. Top-level tree is designed as strict symmetrical structure with topological symmetry and symmetric overhead of wire resources, since the symmetry structure can help achieve zero-skew in theory. In our work, we present an approximate symmetry tree as the optimized top-level tree with the methodology of clustering and topology reconstruction. Considering a skew value bound, the wirelength cost is much reduced. The strategy for building our proposed tree is based on a machine learning-based predictor which can realize the fast analysis of the potential possibilities of routing patterns. Runtime for the tuning process can be much saved compared with traditional simulation method.