A Novel Low-Power Single-step Subranging Open-loop Sigma-Delta ADC

This paper presents a novel subranging ADC using a relaxation Current-Controlled Oscillator (ICO). A simple low-power technique to reduce the quantization error at each sampling edge is proposed. The idea here is to increase the frequency of the oscillator just before the sampling edge to enhance the oversampling-ratio for a small fraction of the sampling period for subranging. This accomplishes a higher Signal-to-Noise Ratio (SNR) performance without the need of running the ICO at a very high frequency all the time. This ADC is inspired by the strategy used by athletes running marathon where they speed-up close to the finish line to resolve clear victory. The complete system is designed in TSMC 180nm CMOS technology. The simulation results show an ENOB of 13.6-bits consuming just 1.9µW of power from a 1.2V supply. A Schreier FoM of 174.2dB and a Walden FoM of 76.5fJ/conversion cycle are accomplished.