Communication architectures for system-on-chip

The analysis of the communication architecture and its associated synthesis process has grown in importance in the era of System-On-Chip (SoC) devices, since one is moving towards more complex systems, made by several processing elements (cores), with heterogeneous behavior. In many cases, the choice for a communication architecture can be the most crucial factor to meet design constraints. This goal of this work is to define and implement algorithms devoted to analyzing and selecting those communication architectures that better match the user defined system constraints, in an integrated design environment.