Design of 1.5V-3GHz CMOS two stages three loops chained VCO

This paper proposes a new delay cell for operating in high frequency and multi chained two stage VCO to improve phase noise performance. The proposed multi-chained architecture is able to reduce a timing jitter or a transition spacing and the newly VCO is operating in high frequency. The PFD circuit designed to prevent fluctuation of charge pump circuit under the locking condition. Simulation results show that the tuning range of proposed VCO is wide at 1.8GHz/spl sim/3.2Ghz and power dissipation is 0.6mW.