Junctionless Multiple-Gate (JLMG) MOSFETs: A Unified Subthreshold Current Model to Assess Noise Margin of Subthreshold Logic Gate

With the quasi-3-D scaling equation, quasi-3-D minimum channel potential, and drift-diffusion model, a unified subthreshold current model for junctionless multiple-gate (JLMG) MOSFETs including quadruple-gate (QG), triple-gate (TG), and omega-gate (
$\Omega \text{G}$
) devices is developed. With this subthreshold current model, the noise margin (NM) behavior of the subthreshold logic gate composed of JLMG MOSFETs is assessed. With the same cross-sectional area of the devices, the QG MOSFET provides the largest NM among the three devices due to its smallest scaling length. On the contrary, the TG MOSFET with the largest scaling length exhibits the smallest NM. The short-channel-degraded NM behavior can be similarly seen in these devices. In terms of design triangle (DT) of subthreshold logic gate, the QG MOSFET can provide the largest DT as opposed to the smallest one supplied by the TG device. The transistor strength balance (TSB) between p-type and n-type JLMG MOSFETs can be adjusted by tuning the gate work function to implement the optimum NM design. Finally, the impact of random doping fluctuation (RDF) on NM degradation is also discussed in this work.